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Preliminary Technical Data
FEATURES Li-Ion Battery Charger Fixed 12,525 V, 12.600 V, or Adjustable Battery Voltage High End-of-Charge Voltage Accuracy 0.4% @ +25 C 0.6% @ 5 C to 55 C 0.75% @ 0 C to 85 C Programmable Charge Current with Rail-to-Rail Sensing System Current Sense with Reverse Input Protection Softstart Charge Current Undervoltage Lockout Boosted Synchronous Drive For External NMOS Programmable Oscillator Frequency Oscillator SYNC Pin Constant Current/Constant Voltage Flag Trickle Charge APPLICATIONS Portable Computers Fast Chargers
High Frequency Switch Mode Li-Ion Battery Charger ADP3804
GENERAL DESCRIPTION
RY NA L I IM ICA EL N PR CH A TE DAT
FUNCTIONAL BLOCK DIAGRAM
BST DRVH SW DRVL PGND CS+ CS BOOSTED SYNCHRONOUS DRIVER AMP 1
The ADP3804 is a complete Li-Ion battery charging IC. The device combines high output voltage accuracy with constant current control to simplify the implementation of ConstantCurrent, Constant-Voltage (CCCV) chargers. The ADP3804 is available in two options. The ADP3804-12.6 guarantees the final battery voltage to 12.6 V 0.6%, the ADP3804-12.5 guarantees 12.525 V 0.6% and the ADP3804 is adjustable using two external resistors to set the battery voltage. The current sense amplifier has rail-to-rail inputs to accurately operate under low drop out and short circuit conditions. The charge current is programmable with a DC voltage on ISET. A second differential amplifier senses the system current across an external sense resistor and outputs a linear voltage on the ISYS pin. The boosted synchronous driver allows the use of two NMOS transistors for lower system cost.
VCC BSTREG
SYS+ SYS
AMP 2
LIMIT
REG
BOOST REGULATOR + SUPPLY REGULATOR UVLO g m1
ISYS
ISET REF SD REFERENCE + BIAS INPUT DIVIDER ADP3804-12.6 ADP3804-12.5 VREF BATTERY ADJUST
BAT
VREF
g m2 OSCILLATOR
ADJ
ADP3804
AGND SYNC CT COMP CCCV
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADP3804-SPECIFICATIONS1 (@ 0 C T 100 C, VCC =16 V, unless otherwise noted)
A
Parameter
Conditions
Symbol
Min
Typ
Max
Units
BATTERY SENSE INPUT ADP3804-12.6
VBAT VBAT VBAT VBAT Input Resistance Input Current TA = +25C 5C TA 55C 0C TA 85C 0C TA 100C Part in Operation Part in Shutdown VBAT VBAT 12.550 12.524 12.505 12.474 400 12.6 12.650 12.676 12.695 12.726 1.0 V V V V kW mA
VBAT
VBAT RBAT IBAT(SD)
500 0.2
BATTERY SENSE INPUT ADP3804-12.5
VBAT VBAT VBAT VBAT Input Resistance Input Current TA = +25C 5C TA 55C 0C TA 85C 0C TA 100C Part in Operation Part in Shutdown VBAT VBAT 12.475 12.450 12.430 12.400 400 12.525 12.575 12.600 12.620 12.650 1.0 V V V V kW mA
VBAT
VBAT RBAT IBAT(SD)
BATTERY SENSE INPUT ADP3804
VBAT VBAT VBAT Input Current
OSCILLATOR
Maximum Frequency2 Frequency Variation3 CT Charge Current 0% Duty Cycle Threshold Maximum Duty Cycle Threshold SYNC Input High SYNC Input Low SYNC Input Current
RY NA L I LIM ICA RE HN P EC ATA TD
TA = +25C 0C TA 85C 0C TA 100C CT = 150 pF fCT fCT ICT @ COMP Pin @ COMP Pin IL = 10 mA CL = 1 nF, DRVL and DRVH DRVL Falling to DRVH Rising, DRVH Falling to DRVL Rising Part in Shutdown, VSW = 12.6 V RON tr , tf tOP
500 0.2
VBAT
VBAT
VBAT
2.490 2.481 2.475
2.500
0.2 1000 215 130
2.510 2.519 2.525 1.0
V V V mA kHz kHz mA V V V V mA W ns ns A
250 150 1.0 2.5
285 170
SYNCH SYNCL ISYNC
2.0 0.2 6 35 50 0.2 0.8 1.0 10
GATE DRIVE
On Resistance Rise, Fall Time Overlap Protection Delay SW Bias Current
1.0
CURRENT SENSE AMPLIFIER Input Common-mode Range Input Differential Mode Range Input Offset Voltage5 Gain5 Input Bias Current Input Offset Current Input Bias Current SYSTEM CURRENT SENSE6 Input Common Mode Range Input Differential Range Input Offset Voltage Input Bias Current, SYS+ Input Bias Current, SYSVoltage Gain Output Range Limit Output Threshold Limit Output Voltage
VCS+ and VCS- VCS4 0 V VCS(CM) VCC 0 V VCS(CM) VCC, Part in Operation 0 V VCS(CM) VCC Part in Shutdown
SYS+ and SYS-
VCS(CM) VCS(DM) VCS(VOS) VCS(IB) VCS(IOS)
0.0 0.0 1.0 25 50 1.0 0.2
4.0
VCC+0.3 V
160
100 2.0 1.0
mV mV V/V A A A
VSYS(CM)
VCC+0.3 V
(VSYS+) - (VSYS-) VSYS(DM) = 0 V, VSYS(CM) = 16 V VSYS(DM) = 0 V, VSYS(CM) = 16 V 10 V VSYS(CM) VCC + 0.3V IL = 1 mA7, VSYS(CM) > 6 V VISYS > VTH(LIMIT), ISINK = 1 mA
VSYS(DM) IB(SYS+) IB(SYS-)
0 1.0 50 25 50 2.5 0.1
48 VISYS 0 VTH(LIMIT) 2.4 VO(LIMIT)
100 2.0 100 50 52 5.0 2.6 0.2
mV mV mA mA V/V V V V
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ADP3804
Parameter Conditions Symbol Min Typ Max Units
ISET INPUT
Charge Current Programming Function Programming Function Accuracy ISET Bias Current 0.0 V < VISET 4.0 V VISET = 4.0 V VISET = 0.50 V, 0.0 V VISET 4.0 V
VISET/VCS -5 -20 IB -4.8 +4.8 4.4
25 1.0 10 0.2 -5.0 +5.0 4.6 0.2
+5 +20 1.0 -5.2 +5.2 1.0
V/V % % mA
ADJ INPUT VBAT Adjustment VBAT Adjustment VBAT Disable Threshold ADJ Bias Current BOOST REGULATOR OUTPUT Output Voltage Output Current ANALOG REGULATOR OUTPUT
Output Voltage Output Current
VADJ = 1 V VADJ = 4 V 1.0 V VADJ 4.0 V
% % V
mA
CL = 0.1 mF
VBSTREG IBSTREG
6.8 3
7.0 5
7.2
V mA
PRECISION REFERENCE OUTPUT Output Voltage Output Current SHUTDOWN (SD)
ON OFF SD Input Current
POWER SUPPLY
ON Supply Current OFF Supply Current UVLO Threshold Voltage UVLO Hysteresis
RY NA L I LIM ICA RE HN P EC ATA TD
CL = 10 nF
VREG
5..8
6.0
6.2
V
IREG
3.0
5.0
mA
VREF IREF
SDH SDL
2.475 0.5
2.0
2.5 1.1
2.525
V mA
V V
0.2 8.0 2.0 6.0 0.3
0.8 1.0 10 10 6.25 0.5
mA
mA
No External Loads No External Loads Turn On Turn Off
ISYON ISYOFF VUVLO
mA
V V
5.75 0.1
CCCV OUTPUT
Output Voltage Low Output Voltage High Constant Current Mode8, VISET = 2.5 V, ISINK = 100 A Constant Voltage Mode9, VISET = 2.5 V 0.1 external 0.4 V V
OUTPUT REVERSE LEAKAGE PROTECTION Leakage Current
1 2 3
VCC = Floating, VBAT = 12.6 V
IDISCH
3.0
10
A
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Guaranteed by design, not tested in production. If SYNC function is used, then fSYNC must be greater than fCT, but less than 120% of fCT. 4 VCS = (VCS+) - (VCS-). 5 Accuracy guaranteed by ISET INPUT, Programming Function Accuracy specification. 6 System current sense is active during shutdown. 7 Load current is supplied through SYS+ pin. 8 VBAT < 95% of final or VCS > 80% of ISET programmed value. 9 VBAT 95% of final and VCS 80% of ISET programmed value. Specifications subject to change without notice.
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ADP3804
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Input Voltage (VCC to GND) . . . . . . . . . . . -0.3 V to +25 V BAT, CS+, CS- to GND . . . . . . . . . . . . -0.3 V to VCC+0.3 V SYS+, SYS- to GND . . . . . . . . . . . . . . . . . . . . -25 V to +25 V BST to PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -4 V to +25 V DRVL to PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V ISET, ADJ, CCCV, SD, SYNC, CT, LIMIT, ISYS TO GND . . . . . . . . . . . . . . . . -0.3 V to +10 V COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3 V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Operating Ambient Temperature Range . . . . . . 0C to 100C q JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W Operating Junction Temperature Range . . . . . 0C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . +300C
NOTES *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. qJA is specified for worst case conditions with device soldered on a circuit board.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Mnemonic VCC SYS- SYS+ ISYS LIMIT CT SYNC REG REF SD COMP
Function Supply Voltage. Negative System Current Sense Input. Positive System Current Sense Input. System Current Sense Output. System Current Sense Limit Output. Oscillator Timing Capacitor. Oscillator Synchronization Pin. 6.0 V Analog Regulator Output. 2.5 V Precision Reference Output. Shutdown Control Input. External Compensation Node. Constant Current/Constant Voltage Output. Analog Ground. Battery Sense Input. 2.5 V for ADP3804, 12.525 V for ADP380412.5 or 12.6 V for ADP3804-12.6 Battery Voltage Adjust Input. Charge Current Program Input. Negative Current Sense Input. Positive Current Sense Input. Power Ground. Low Drive Output switches between REG and PGND. 7.0 V Regulator Output for Boost. Floating Bootstrap Supply for DRVH. High Drive Output switches between SW and BST. Buck Switching Node Reference for DRVH.
ORDERING GUIDE
Model ADP3804JRU ADP3804JRU-12.5 ADP3804JRU-12.6
Battery Voltage Adjustable 12.525 V 12.600 V
PIN CONFIGURATION
24 Lead TSSOP
VCC 1 SYS- 2 SYS+ 3 ISYS 4 ADP3804
RY NA L I IM ICA EL N PR CH A TE DAT
CCCV Package Description Package Option AGND BAT TSSOP-24 RU-24 TSSOP-24 TSSOP-24 RU-24 RU-24 15 17 18 19 ADJ CS- 16 ISET CS+ PGND DRVL BSTREG BST DRVH SW
24 SW 23 DRVH 22 BST
20 21 22 23 24
TOP VIEW 21 BSTREG LIMIT 5 (Not to Scale) 20 DRVL CT 6 SYNC 7 REG 8 19 PGND 18 CS+ 17 CS- 16 ISET 15 ADJ 14 BAT 13 AGND
REF 9 SD 10 COMP 11 CCCV 12
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADP3804
RSS1 10m Q1 IRF7807 R13 10 C14 2.2F VCC BST L1 22H C16 + Q2 IRF7807D2 220F C9 0.1F DRVH RCS 50m R3 249 C13 22nF R4 249 C1 470nF SYS+ SYSR1 10 R2 10 C2 470nF ISYS SYSTEM DC/DC
VIN +
C15 220F
BATTERY 12.6V
SW
DRVL
PGND
CS+
CS-
BOOSTED SYNCHRONOUS DRIVER
+ AMP 1
+ AMP 2 *R11 412k 0.1%
BSTREG 7.0V C10 0.1F SD
VREF + VREG UVLO BIAS
VREF 2.5V g m1
LIMIT
ISET ADP3804-12.6 BAT SD *R12 102k 0.1%
LOGIC CONTROL
CCCV
**R7 100k
ADP3804
AGND
REG 6.0V
C17 100nF
* ADP3804-12.6: R11 = SHORT, R12 = OPEN ** R7, OPEN IF CCCV FUNCTION IS NOT USED
THEORY OF OPERATION
Y AR IN AL IM IC EL HN PR EC TA T DA
g m2 OSCILLATOR VREF REF 2.5V SYNC CT C7 200pF C6 200pF COMP C8 1F ADJ R8 56
ADP3804-12.5
R5 6.81k R6 7.5k
Figure 1. Typical Application
The ADP3804 combines a boosted synchronous switching driver with programmable current control and accurate final battery voltage control in a Constant Current, Constant Voltage (CCCV) Li-Ion battery charger. High accuracy voltage control is needed to safely charge Li-Ion batteries, which are typically specified at 4.2 V 1% per cell. For a typical notebook computer battery pack, three cells are in series giving a total voltage of 12.6 V. The ADP3804 is available in three versions, a fixed 12.525 V output, a fixed 12.6 V output and an adjustable output. The adjustable output is useful for charging batteries with slightly different chemistry that result in a final battery voltage slightly higher or lower than 4.2 V/ cell. Another requirement for safely charging Li-Ion batteries is accurate control of the charge current. The actual charge current depends on the number of cells in parallel within the battery pack. Typically this is in the range of 2 A to 3 A. The ADP3804 provides flexibility in programming the charge current over a wide range. An external resistor is used to sense the charge current and this voltage is compared to a DC input voltage. This programmability allows the current to be changed during charging. For example, the charge current can be reduced for trickle charging. The synchronous driver provides high efficiency when charging at high currents. Efficiency is important mainly to reduce the REV. PrI -5-
amount of heat generated in the charger, but also to stay within the power limits of the AC adapter. With the addition of a boosted high side driver, the ADP3804 drives two external power NMOS transistors for a simple, lower cost power stage. The ADP3804 also provides an uncommitted current sense amplifier. This amplifier provides an analog output pin for monitoring the current through an external sense resistor. The amplifier can be used anywhere in the system that high side current sensing is needed.
Charge Current Control
AMP1 in Figure 1 has a differential input to amplify the voltage drop across an external sense resistor RCS. The input common mode range is from ground to VCC allowing current control in short circuit and low drop-out conditions. The gain of AMP1 is internally set to 25 V/V for low voltage drop across the sense resistor. During CC mode, gm1 forces the voltage at the output of AMP1 to be equal to the external voltage at the ISET pin. By choosing RCS and VISET appropriately, a wide range of charge currents can be programmed:
ICHARGE =
VISET 25 xRCS
(1)
ADP3804
Typical values of RCS are in the range from 25 mW to 50 mW, and the input range of ISET is from 0 V to 4 V. If, for example, a 2 A charger is required, then RCS could be set to 50 mW and VISET = 2.5 V. The power dissipation in RCS should be kept below 500 mW. In this example, the power is a maximum of 200 mW. Once RCS has been chosen, the charge current can be adjusted during operation with VISET. Lowering VISET to 125 mV gives a charge current of 100 mA for trickle charging. Components R3, R4, and C13 provide high frequency filtering for the current sense signal.
Final Battery Voltage Control
approximately 200 nsec to ensure that the boost capacitor is always charged. This off time sets the maximum duty cycle. For example, a 200 kHz frequency (5 sec period) gives a maximum duty cycle of 96%. The oscillator frequency is set by the external capacitor at the CT pin and the internal current source of 150 A according to the following formula:
fOSC =
150mA 2 x CT x 1.5V
(4)
As the battery approaches its final voltage, the ADP3804 switches from CC mode to CV mode. The change is achieved by the common output node of gm1 and gm2. Only one of the two outputs controls the voltage at the COMP pin. Both amplifiers can only pull down on COMP, such that when either amplifier has a positive differential input voltage, its output is not active. For example, when the battery voltage, VBAT, is low, gm2 does not control VCOMP. When the battery voltage reaches the desired final voltage, gm2 takes control of the loop, and the charge current is reduced.
A 200 pF capacitor sets the frequency to 250 kHz. The frequency can also be synchronized to an external oscillator by applying a square wave input on SYNC. The SYNC function is designed to allow only increases in the oscillator frequency. The fSYNC should be no more than 20% higher than fOSC. The duty cycle of the SYNC input is not important and can be anywhere between 5% and 95%.
7V Boost Regulator
Amplifier gm2 compares the battery voltage to the internal reference voltage of 2.5 V. In the case of the ADP3804-12.5 and ADP3804-12.6, an internal resistor divider sets the final battery voltage to 12.6 V. In contrast, the ADP3804 requires external, precision resistors. The divider ratio should be set to divide the desired final voltage down to 2.5 V at the BAT pin:
R11 VBATTERY = -1 R12 2.5V
These resistors should be high impedance to limit the battery leakage current. Alternatively, an external NMOS can be added in series with R12 to turn off during shutdown. In the case of the ADP3804-12.5 and ADP3804-12.6, an internal MOSFET disconnects the internal divider to reduce the leakage current into BAT to less than 1 A during shutdown. If the ADP380412.5 or ADP3804-12.6 is used, then R11 should be shorted and R12 open. The reference and internal resistor divider are referenced to the AGND pin, which should be connected close to the negative terminal of the battery to minimize sensing errors.
Final Battery Voltage Adjust
RY NA L I IM ICA EL N PR CH A TE DAT
(2)
The driver stage is powered by the internal 7V boost regulator, which is available at the BSTREG pin. Because the switching currents are supplied by this regulator, decoupling must be added. A 0.1 F capacitor should be placed close to the ADP3804, with the ground side connected close to the power ground pin, PGND. This supply is not recommended for use externally due to high switching noise.
Boosted Synchronous Driver
The PWM comparator controls the state of the synchronous driver. A high output from the PWM comparator forces DRVH on and DRVL off. The drivers have an ON resistance of approximately 5 W for fast rise and fall times when driving external MOSFETs. Furthermore, the boosted drive allows an external NMOS transistor for the main switch instead of a PMOS. A boost diode is internally connected between BSTREG and BST, and a boost capacitor of 0.1 F must be added externally between BST and SW. The voltage between BST and SW is typically 6 V. The DRVL pin switches between BSTREG and PGND. The 7 V output of BSTREG drives the external NMOS with high VGS to lower the ON resistance. PGND should be connected close to the source pin of the external synchronous NMOS. When DRVL is high, this turns on the lower NMOS and pulls the SW node to ground. At this point, the boost capacitor is charged up through the internal boost diode. When the PWM switches high, DRVL is turned off and DRVH turns on. DRVH switches between BST and SW. When DRVH is on, the SW pin is pulled up to the input supply (typically 16 V), and BST rises above this voltage by approximately 6 V. Overlap protection is included in the driver to ensure that both external MOSFETs are not on at the same time. When DRVH turns off the upper MOSFET, the SW node goes low due to the inductor current. The ADP3804 monitors the SW voltage, and turns on DRVL when SW goes below 1 V. If, under low current loads, the SW voltage does not drop below 1 V, DRVL will turn on after time-out of 200 nsec. When DRVL turns off, an internal timer adds a delay of 50 nsec before turning DRVH on.
The ADJ pin provides an analog input to adjust the final battery voltage by 5%. Figure 2 shows the control curve for this amplifier. Above the threshold voltage of 4.6 V, the amplifier is turned off. Thus, to disable this function, ADJ should be connected to REG. In the linear range between 1 V and 4 V, the percentage change in VBAT is a function VADJ as follows:
DVBAT % = 100 x
VADJ - 2.5V 30
(3)
This percent change is the same for the ADP3804 (2.5 V output) and the ADP3804-12.6.
Oscillator and PWM
The oscillator generates a triangle waveform between 1 V and 2.5 V, which is compared to the voltage at the COMP pin, setting the duty cycle of the driver stage. When VCOMP is below 1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches its maximum. The ADP3804 forces a minimum off time of -6-
REV. PrI
ADP3804
2.5 V Precision Reference UVLO
The voltage at the BAT pin is compared to an internal precision, low temperature drift reference of 2.5 V. The reference is available externally at the REF pin. This pin should be bypassed with a 100 pF capacitor to the analog ground pin, AGND. The reference can be used as a precision voltage externally. However, the current draw should not be greater than 100 A, and no noisy, switching type loads should be connected.
6 V Regulator
The 6 V regulator supplies power to most of the analog circuitry on the ADP3804. This regulator should be bypassed to AGND with a 10 nF capacitor. This reference has a 3 mA source capability to power external loads if needed.
CCCV
Under-Voltage Lock-Out, UVLO, is included in the ADP3804 to ensure proper start-up. As VCC rises above 1 V, the reference and regulators will track VCC until they reach their final voltages. However, the rest of the circuitry is held off by the UVLO comparator. The UVLO comparator monitors both regulators to ensure that they are above 5 V before turning on the main charger circuitry. This occurs when VCC reaches 6 V. Monitoring the regulator outputs makes sure that the charger circuitry and driver stage have sufficient voltage to operate normally. The UVLO comparator includes 300 mV of hysteresis to prevent oscillations near the threshold.
Startup Sequence
An open drain output is available to signal when the ADP3804 switches from CC to CV charging. An external pull-up resistor of 100 kW to REG or other pull-up voltage is required for this function. If the CCCV signal is not needed, the pin should be left open. The CCCV function uses two comparators to monitor the battery voltage and the charge current. In order for the CCCV pin to go high, signaling CV mode, the battery voltage must be higher than 95% of its final value, and the current must be less than 80% of its programmed value. If the battery voltage is less than 95% then CCCV will be low regardless of the actual current flowing. This is to prevent a false output during startup when the current is low.
System Current Sense
An uncommitted differential amplifier is provided for additional high side current sensing. This amplifier, AMP2, has a fixed gain of 50 V/V from the SYS+ and SYS- pins to the analog output at ISYS. ISYS has a 1 A source capability to drive an external load. The common mode range of the input pins is from 4 V to VCC. This amplifier is the only part of the ADP3804 that remains active during shutdown. The power to this block is derived from the bias current on the SYS+ and SYS- pins. A separate comparator is included to provide a flag when the voltage at ISYS rises above 2.5 V. The open drain output is capable of sinking 1 A when the threshold is exceeded. This comparator is turned off during shutdown to conserve power.
Shutdown
Y AR IN AL IM IC EL HN PR EC TA T DA
t DELAY =
Loop Feed Forward
During a startup from either SD going high or VCC exceeding the UVLO threshold, the ADP3804 initiates a soft-start sequence. The soft-start timing is set by the compensation capacitor at the COMP pin and an internal 40 A source. Initially, both DRVH and DRVL are held low until VCOMP reaches 1 V. This delay time is set by:
CCOMP - 1V 40mA
(5)
For a 1 F COMP capacitor, tDELAY is 25 msec. After this initial delay, DRVL is turned on first for one period to give the boost capacitor time to charge up. The duty cycle then ramps up to its final value with the same ramp rate given for tDELAY. For example, if VIN is 16 V and the battery is 10 V when charging is started, the duty cycle will be approximately 65%, corresponding to a VCOMP of ~2 V. The time for the duty cycle to ramp from 0% at VCOMP = 1 V to 65% at VCOMP = 2 V is approximately 25 msec. As the startup sequence discussion shows, the response time at COMP is slowed by the large compensation capacitor. To speed up the response, two comparators can quickly feed forward around the normal control loop and pull the COMP node to ground to limit any over shoot in either short circuit or overvoltage conditions. The over-voltage comparator has a trip point set to 20% higher than the final battery voltage. The over-current comparator threshold is set to 200 mV across the CS pins, which is 25% above the maximum programmable threshold. When these comparators are tripped, a normal softstart sequence is initiated. This will give 0% duty cycle with DRVH off and DRVL on. The over-voltage comparator is valuable when the battery is removed during charging. In this case, the current in the inductor causes the output voltage to spike up, and the comparator limits the maximum voltage. Neither of these comparators affect the loop under normal charging conditions.
A high impedance CMOS logic input is provided to turn off the ADP3804. When the voltage on SD is less than 0.8 V, the ADP3804 is placed in low power shutdown. With the exception of the system current sense amplifier, AMP2, all other circuitry is turned off. The reference and regulators are pulled to ground during shutdown and all switching is stopped. During this state, the supply current is less than 10 A. Also, the BAT, CS+, CS-, and SW pins go to high impedance to minimize current drain from the battery.
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